MPC5604C
Overview
- Single issue, 32-bit CPU core complex (e200z0) - Compliant with the Power Architecture® embedded category - Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction.
- Up to 512 KB on-chip code flash supported with the flash controller and ECC
- 64 (4 × 16) KB on-chip data flash memory with ECC
- Up to 48 KB on-chip SRAM with ECC
- Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity
- Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources
- Frequency modulated phase-locked loop (FMPLL)
- Crossbar switch architec
