MPC5674F
Key Features
- Dual issue, 32-bit CPU core plex (e200z7) – pliant with the Power Architecture® embedded category – 16 KB I-Cache and 16 KB D-Cache – Includes an instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction – Includes signal processing extension (SPE2) instruction support for digital signal processing (DSP) and single-precision floating point operations
- 4 MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation
