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MPC7410 - RISC Microprocessor

General Description

29 System Design Information

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Key Features

  • ch processing unit.
  • Four instructions fetched per clock.
  • One branch processed per cycle (plus resolving two speculations).
  • Up to one speculative stream in execution, one additional speculative stream in fetch.
  • 512-entry branch history table (BHT) for dynamic prediction.
  • 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots Dispatch unit.
  • Full hardware detection of dependencies (resolved i.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Freescale Semiconductor Technical Data MPC7410EC Rev. 6.1, 11/2007 MPC7410 RISC Microprocessor Hardware Specifications www.DataSheet4U.com The MPC7410 is a PowerPC™ reduced instruction set computing (RISC) microprocessor. This document describes pertinent electrical and physical characteristics of the MPC7410. For functional characteristics of the processor, refer to the MPC7410 RISC Microprocessor User’s Manual. To locate any published errata or updates for this document, refer to the web site at http://www.freescale.com. 1 Overview 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 General Parameters . . . . . . . . . . . . . . .