MPC8250 Datasheet | Freescale Semiconductor

Features G2 dual-issue integer core - A core version of the MPC603e microprocessor - System core microprocessor supporting frequencies of 150- 200 MHz - Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm - Power PC architecture-pliant memory management unit (MMU) - mon on-chip processor (COP) test interface - High-performance (4.4- 5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at 200 MHz) The following is an overview of the MPC8250 feature set: For More Information On This Product, Go to: .freescale. Freescale Semiconductor, Inc. Features - - - - Freescale Semiconductor, Inc... - - - Supports bus snooping for cache coherency - Floating-point unit (FPU) Low-power (less than 2.0 W in Hi P4) See the MPC8260 Power Consumption Calculator on the Smart Networks Web Page for the 8260 Family at .motorola.. Separate power supply for internal logic (1.8 V in Hi P4) and for I/O (3.3 V) Separate PLLs for G2 core and for the CPM - G2 core and CPM can run at different frequencies for power/performance optimization - Internal G2 core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios - Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus - Bus supports multiple master designs - Supports single- and four-beat burst transfers - 64-,...