MPC8533E Description
93 System Design Information . 102 Device Nomenclature . 111 Document Revision History.
MPC8533E Key Features
- High-performance 32-bit Book E-enhanced core built on Power Architecture™ technology
- 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a p
- Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit
- Double-precision floating-point APU. Provides an instruction set for do