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MPC8533E Datasheet Powerquicc Iii Integrated Processor

Manufacturer: Freescale Semiconductor (now NXP Semiconductors)

Overview: Freescale Semiconductor Technical Data Document Number: MPC8533EEC Rev. 3, 11/2009 www.DataSheet4U.com MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications 1 MPC8533E Overview Contents MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Enhanced Three-Speed Ethernet (eTSEC), MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Programmable Interrupt Controller . . . . . . . . . . . . . 51 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Description

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Key Features

  • Figure 1 shows the major functional units within the device. 1.1 Key Features 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. The following list provides an overview of the device feature set:.
  • High-performance 32-bit Book E.
  • enhanced core built on Power Architecture™ technology:.
  • 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate lock.

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