MSC8154 Datasheet | Freescale Semiconductor

Freescale Semiconductor Data Sheet Document Number: MSC8154 Rev. 7, 08/2013 Quad-Core Digital Signal Processor FC-PBGA- 783 29 mm × 29 mm - Four Star Core SC3850 DSP subsystems, each with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support. - Chip-level arbitration and switching system (CLASS) that provides full fabric non-blocking arbitration between the cores and other initiators and the M2 memory, shared M3 memory, DDR SRAM controllers, device configuration control and status registers, MAPLE-B, and other targets. - 1056 Kbyte 128-bit wide M3 memory, 1024 Kbytes of which can be turned off to save power. - 96 Kbyte boot ROM. - Three input clocks (one global and two differential). - Five PLLs (three global and two Serial Rapid IO PLLs). - Multi-Accelerator Platform Engine for Baseband (MAPLE-B) with a programmable system interface, Turbo decoding, Viterbi decoding, and FFT/i FFT and DFT/i DFT processing. MAPLE-B can be disabled when not required to reduce overall power consumption. - Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 and DDR3. - DMA controller with 32 unidirectional channels supporting 16 memory-to-memory channels with up to 1024 buffer descriptors per channel, and programmable priority, buffer, and multiplexing configuration. It is optimized for DDR SDRAM. - Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 62.5 Mbps data rate for each TDM link, and with glueless interface to E1 or T1 framers that can interface with...