FEATURES
List................................... 6 MPC5534 Memory Map ................................ 18 Detailed FEATURES
.......................................... 21 Chip Configuration......................................... 30 Documentation .............................................. It is 100% user mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E architecture has enhancements that improve the PowerPC architecture’s fit in embedded applications. This core also has additional instructions, including digital signal processing (DSP) instructions, beyond the classic PowerPC instruction set. The host processor core of the MPC5534 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to achieve significant code size footprint reduction. © Freescale Semiconductor, Inc., 2005. All rights reserved. 4U.com The MPC5534 has a single level of memory hierarchy consisting of 64-Kbyte on-chip SRAM and 1 Mbyte of internal Flash memory.
