F497 Datasheet | Fujitsu Media Devices Limited

feature is the on-chip CAN Interface, which conforms to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme, including 8 message buffers, and so offering more functions than a normal full CAN approach. With the new 0.5 mm CMOS technology, Fujitsu now also offers on-chip FLASH-ROM program memory. An internal voltage booster removes the necessity for a second programming voltage. An on-chip voltage regulator provides 3V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 62.5 nsec instruction cycle time from an external 4 MHz clock. A 32k Hz Subsystem clock has been included for power saving modes and real time measurement. There are 2 on-chip UART’s, which also provide synchronous munication modes. Furthermore the MCU Features an 8 channel ADC, 8 channel External interrupt controller, two 16 bit PPG channels, 4 channel Input Capture Unit and a 16-bit free running I/O-timer. MB90495 Series Data Sheet (Advance Information) 1 / 40 FME EMDC June 19, 2000 MB90495 Series 2. Features - - - - - - - - - - - - - - 16-bit core CPU; 4MHz external clock (16 MHz internal, 62.5 ns instruction cycle time) 32k Hz Subsystem Clock 0.5 mm CMOS Technology Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures 64 KB FLASH ROM; supports automatic programming, 10.000 erase cycles, 10 year data retention time and no second programming voltage required 2 KB static RAM FULL-CAN interface; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) 2 UART’s; both offering synchronous munication modes. Powerful interrupt functions (8 programmable priority levels; 8 external interrupts) I/O Timer A/D Converter: 8 channel analogue inputs (Resolution 10 bits or 8 bits) ICU (Input capture) 16bit - 4ch PPG (Programmable Pulse Generator) 16bit - 2ch; Can be...