CA91 Description
AccelArrayTM is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed mon 3 to 4 metal layers out of 6 to 7 layers. By using 0.11 µm CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681...
CA91 Key Features
- High-speed, large scale ASIC produced in short development time: TAT = One third pared with Standard Cell ASICs (target
- Uses an architecture that simplifies physical design tasks
- Pre-designed mon masters with IR-drop free
- Pre-designed test circuit insertion to reduce test synthesis tasks
- Uses a dedicated timing-driven layout tool to reduce development time
- Signal Integrity Free (pre-designed main clock trees without design verifications)
- Max built-in gate number : 6,000,000 gates or more
- Technology : 0.11 µm Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
- Internal cells support high-speed operation
- Power supply voltage : +1.2 V ± 0.1 V/2.5 V ± 0.2 V (Dual power supply. Needs 1.5 V power supply during using HTSL.)