Description
AccelArrayTM
is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers.
Features
- High-speed, large scale ASIC produced in short development time: TAT = One third compared with Standard Cell ASICs (target value).
- Uses an architecture that simplifies physical design tasks.
- Pre-designed common masters with IR-drop free.
- Pre-designed test circuit insertion to reduce test synthesis tasks.
- Uses a dedicated timing-driven layout tool to reduce development time.
- Signal Integrity Free (pre-designed main clock trees without de.
CA91 Datasheet
