MB86626 Overview
The analog circuitry consists of two 15-bit DACs with associated anti-imaging filters, two 15-bit ADCs with anti-aliasing filters and two programmable gain summing amplifiers (PGA). A clock multiplier and bandgap reference are incorporated on-chip. A configurable data interface allows for high speed data transfer of the receive/transmit data, while a serial interface is provided for control and configuration. All analog signal paths are differential. This highly integrated device reduces the number of ponents required for the line interface to a transmit line driver and a small number of passive ponents. Analog echo cancellation at the RT attenuates the transmit echo at the input of the PGA allowing higher gain before the ADC. This gives lower receiver noise on long lines. A functional block diagram is shown in Figure 1. The device is manufactured in a 0.35µm CMOS process with Triple...
MB86626 Key Features
- Integrates all active circuits except transmit line driver
- Programmable for G.dmt (1 channel) or G.lite (2 channel)
- Low power, 3.3V operation
- from 235mW/ch (2 channel CO G.lite) to 525mW (RT G.dmt)
- Integrated filters and 15-bit A/D & D/A converters
- 0 to +38 dB AGC range for receive channel
- Supports analog and digital echo cancellation
- Excellent SFDR and input noise
- 0.35µm CMOS technology with Triple Well
- Industrial temperature range (-40 °C to +85 °C)