MB91133
Key Features
- CPU * * * * * * * * * *
- 32-bit RISC (FR30) , load/store architecture, 5-level pipeline Multi-purpose register : 32 bits × 16 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes Function entry / exit instruction, multi load / store instruction of register details : High-level language handling instruction Register interlock function : Simplification of assembler description Branch instruction with delay slot : Reduction in overheads in case of branching Multiplier is built-in / supported at instruction level. Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles Interruption (saving PC and PS) : 6 cycles, 16 priority levels (Continued) s PACKAGES 144-pin plastic FBGA 144-pin plastic LQFP (BGA-144P-M01) (FPT-144P-M08) DataSheet 4 U .com
