MB91F369GA Datasheet | Fujitsu Semiconductor Limited

DESCRIPTION The Fujitsu MB91360G series is a standard microcontroller containing a wide range of I/O peripherals and bus control functions. The MB91360G series features a 32-bit RISC CPU (FR50 series) core and is suitable for embedded control applications requiring high-performance and high-speed CPU processing. The MB91360G series also contains up to 4 Kbytes instruction cache memory and other internal memories to improve the execution speed of the CPU. s FEATURES - Execution time : down to 15.6 ns (64 MHz) - FR50 series CPU : RISC architecture The CPU has a general-purpose register architecture with improved numeric implementation whereby a wide range of delayed branch instructions reduces losses in execution time due to pipeline breaks. Bit manipulation instructions and memory access instructions have been enhanced resulting in improved code efficiency and execution speed for control implementation. - A five-stage pipeline structure provides high-speed processing (one instruction per cycle) - 32-bit linear address space : 4 Gbytes - Fixed 16-bit instruction size (basic instructions) - High-speed multiplication/step division - High-speed interrupt processing (6 cycles) - General-purpose registers : 16 × 32 bits (Continued) s PACKAGE 401-pin Ceramics PGA 208-pin plastic QFP 160-pin plastic QFP (PGA-401C-A02) (FPT-208P-M04) (FPT-160P-M15) Data Sheet 4 U . .. MB91360G Series (Continued) - External bus interface unit with a wide range of functions Divides the external memory space into a maximum of eight areas. Chip select signal setting, data bus width selection (8, 16, 32-bit) , and area size can be specified for each area. - Address bus up to 32 bit wide - Programmable auto-wait function - Internal instruction cache The MB91360G series contains up to 4-Kbyte instruction cache to improve the execution speed of external programs. - Two-way set associative caching - DMAC Direct memory access (DMA) can be used to perform various types of data transfer without...