MBM29F004TC Datasheet PDF - Fujitsu Media Devices (MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT Specs

MBM29F004TC - (MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT

This page provides the datasheet information for the MBM29F004TC, a member of the MBM29F004BC (MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT family.

Datasheet Summary

Description

The MBM29F004TC/BC is a 4 M-bit, 5.0 V-Only Flash memory organized as 512 K bytes of 8 bits each.

The MBM29F004TC/BC is offered in a 32-pin TSOP (1) and 32-pin QFJ (PLCC) packages.

This device is designed to be programmed in-system with the standard system 5.0 V VCC supply.

Features

a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. The MBM29F004TC/BC is erased when shipped from the factory. The MBM29F004TC/BC device also features hardware sector group protection. This feature will disable both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. Fujitsu has implemented an Erase Suspend feature that enables.

Datasheet Details

Part number	MBM29F004TC
Manufacturer	Fujitsu Media Devices
File Size	489.39 KB
Description	(MBM29F004BC/TC) FLASH MEMORY CMOS 4 M (512 K X 8) BIT
Datasheet	MBM29F004TC Datasheet
Additional preview pages of the MBM29F004TC datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20876-3E FLASH MEMORY CMOS 4 M (512 K × 8) BIT MBM29F004TC/004BC-70/-90 s DESCRIPTION The MBM29F004TC/BC is a 4 M-bit, 5.0 V-Only Flash memory organized as 512 K bytes of 8 bits each. The MBM29F004TC/BC is offered in a 32-pin TSOP (1) and 32-pin QFJ (PLCC) packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F004TC/BC offers access times between 70 ns and 90 ns allowing operation of high-speed microprocessors without wait states.

Published: Jul 30, 2007 |