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MBM29F040C - 4M (512K X 8) BIT FLASH MEMORY

Datasheet Summary

Description

The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each.

The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package.

This device is designed to be programmed in-system with the standard system 5.0 V VCC supply.

Features

  • Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN.
  • Normal Bend Type, PFTR.
  • Reversed Bend Type) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase arc.

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Datasheet Details

Part number MBM29F040C
Manufacturer Fujitsu Media Devices
File Size 437.81 KB
Description 4M (512K X 8) BIT FLASH MEMORY
Datasheet download datasheet MBM29F040C Datasheet
Additional preview pages of the MBM29F040C datasheet.

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20842-4E FLASH MEMORY CMOS 4M (512K × 8) BIT MBM29F040C-55/-70/-90 s FEATURES • • • Single 5.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture 8 equal size sectors of 64K bytes each Any combination of sectors can be concurrently erased. Also supports full chip erase.
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