MBM29F040C Datasheet | Fujitsu Semiconductor Limited

FEATURES - - - Single 5.0 V read, program and erase Minimizes system level power requirements patible with JEDEC-standard mands Uses same software mands as E2PROMs patible with JEDEC-standard byte-wide pinouts 32-pin PLCC (Package suffix: PD) 32-pin TSOP(I) (Package suffix: PF) 32-pin TSOP(I) (Package suffix: PFTN - Normal Bend Type, PFTR - Reversed Bend Type) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture 8 equal size sectors of 64K bytes each Any bination of sectors can be concurrently erased. Also supports full chip erase. Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector Embedded Program™ Algorithms Automatically writes and verifies data at specified address Data Polling and Toggle Bit feature for detection of program or erase cycle pletion Low VCC write inhibit ≤ 3.2 V Sector protection Hardware method disables any bination of sectors from write or erase operations Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device .. - - - - - - - - - Embedded Erase™, Embedded Program™ and Express Flash™ are trademarks of Advanced Micro Devices, Inc. MBM29F040C-55/-70/-90 s PACKAGE 32-pin Plastic QFJ (PLCC) Marking Side (LCC-32P-M02) 32-pin Plastic TSOP (I) Marking Side 32-pin Plastic TSOP (I) Marking Side (FPT-32P-M24 - Assembly: Malaysia) (FPT-32P-M25 - Assembly: Malaysia) MBM29F040C-55/-70/-90 s GENERAL DESCRIPTION The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. A 12.0 V VPP is not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29F040C offers access times 55 ns and 90 ns, allowing operation of high-speed microprocessors without...