Fujitsu MB1412A
LS-TTL Error Checking and Correction Circuit
| Part No. | MB1412A |
|---|---|
| Datasheet | MB1412A Download |
| Manufacturer |  Fujitsu |
| Description | LS-TTL Error Checking and Correction Circuit |
| Buy | Stock & Price |
ABSOLUTE MAXIMUM RATINGS
are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3-23 1111111111111111111111111111111111111111111111111111 FUJITSU 111111111111111111111111111111111111111111111I111111 MB 1412A Fig.l MB 1412A BLOCK DIAGRAM 510 I SI5 CIO I CI5 RDO I RD7 WDO I WD7 STBC -If------I RVC02} _-+-_ _-1 RVC36 so I 56 SOD I 505 COO I C05 DO I D7 r---------~RVC r---------~REl RD: Read Data Buffer SG: Syndrome Generator WD: Write Data Buffer DS: Data Selector CG: Check●bit Generator CC: Check-bit Corrector 5: Syndr'ome I nput Buffer DC: Data Corrector SD: Syndrome Decoder/locator FUNCTIONS OF BLOCK ELEMENTS RD (Read Data Buffer) Input buffer gate for memory read data. SG (Syndrome Generator) Generates syndrome for the data to be checked in the read data buffer. WD (Write Data Buffer) Input buffer gate for memory write data.
