Datasheet4U Logo Datasheet4U.com

MB85R1002A - 1 M Bit (64 K x 16)

General Description

The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words × 16 bits of nonvolatile memory cells created using ferroelectric process and silicon gate CMOS process technologies.

Key Features

  • Bit configuration Read/write endurance Operating power supply voltage Operating temperature range Data retention LB and UB data byte control Package : 65,536 words × 16 bits : 1010 times : 3.0 V to 3.6 V :.
  • 40 °C to + 85 °C : 10 years ( + 55 °C) : 48-pin plastic TSOP (1) Copyright©2011.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MB85R1002 Memory FRAM Fujitsu Media Devices
MB85R1001 1 M Bit (128 K X 8) Fujitsu Media Devices
MB85R256 Memory FRAM Fuji Electric
MB85R256H Memory FRAM CMOS 256 K (32 K X 8) Bit Fujitsu Media Devices
MB805 Single Phase Bridge Rectifier Micro Commercial Components

Other Datasheets by Fujitsu Semiconductor Limited

Part Number Description
MB85R1001A 1 M Bit (128 K x 8)
MB85R2001 Memory FRAM CMOS
MB85R2002 Memory FRAM CMOS
MB85R256F Memory FRAM
MB85R4001A Memory FRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
FUJITSU SEMICONDUCTOR DATA SHEET DS501-00004-0v01-E Memory FRAM CMOS 1 M Bit (64 K × 16) MB85R1002A ■ DESCRIPTIONS The MB85R1002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words × 16 bits of nonvolatile memory cells created using ferroelectric process and silicon gate CMOS process technologies. The MB85R1002A is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002A can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R1002A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.