DESCRIPTION
Conforming to the SPARC *2 architecture, the MB86830 series is upward codecompatible with the conventional products in the SPARClite family. The independent instruction bus and internal data bus serve as high-bandwidth interfaces between the IU (integer unit) and caches. The MB86830 series also contains an internal multiplier circuit that facilitates interfacing with external devices, thereby providing high performance with continuous cache hits. The DRAM controller supports both of EDO and fast-page mode DRAMs. The interrupt controller (IRC) supports eight channels of interrupts, allowing a trigger mode and mask to be set for each of the channels. To get the most out of the system with a minimum number of external circuits, the MB86830 series supports chip select output, programmable wait state generator, and page mode DRAM interfaces. The combination of these features of the MB86830 series achieves high levels of speed, flexibility, and efficiency, making it a line of ide...
Fujitsu
