MB87L2250 Datasheet | Fujitsu Semiconductor Limited

Product Profile - MPEG2 Transport, Video and Audio Decoder with integrated 32-Bit RISC CPU OVERVIEW Fujitsu’s MB87L2250 is a single chip MPEG video and audio decoder which also includes the transport demultiplexer and 32-Bit RISC CPU. This offers a very cost effective high integrated solution for set top box applications. MPEG decoding and transport demultiplexing are implemented in hardware. The on-chip CPU, operating at 54 MHz, is fully available for customer application software, for example the EPG function. The MB87L2250 uses a 2.5 frame architecture which requires only one 16 Mbit SDRAM memory for MPEG decoding, OSD and section data buffering. In addition the chip provides advanced Features like letterbox format conversion or teletext insertion into the VBI. Plastic Flat Package FPT-208P-M01 October 1998 Edition 1.1 Features - - - - - - - - - - - - - - - - - - RISC CPU integrated (32-bit) 1 KByte I-Cache 2.5 Frame Architecture Only 16 Mbit SDRAM required 32 PID’s supported Hardware Filter for PID and Sections IR Receiver DVB Descrambler Memory Save Mode to reduce Picture Memory Teletext Insertion in VBI Letterbox Format Conversion 3:2 Pull Down FR30 / 68k / SPARClite Processor Interface I2C Interface Two Smart Card Interfaces 2, 4, 6 or 8 Bit OSD 16 Programmable General Purpose I/O’s Automatic Clock Recovery Pin Assignment 156 157 105 104 Index 208 1 52 Fujitsu Mikroelektronik Gmb H Proprietary Information Confidential Product Profile October 1998 Edition 1.1 - MPEG2 Decoder 1. Chip Architecture Figure 1 shows the chip architecture of Demultiplexer and Audio/Video Decoder MB87L2250, which is dedicated for DVB pliant applications (DVB-S, DVB-C, DVB-T). DVB Descrambler MPEG Video Demodulation Module Transport Demultiplexer) Graphics/Video Controller (OSD, Teletext) PAL / NTSC Encoder MPEG Audio Audio...