MB96F656 Datasheet | Fujitsu Semiconductor Limited

DESCRIPTION MB96650 series is based on FUJITSU’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements pared to the previous generation include significantly improved performance even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. - : These devices are under development and specification is preliminary. These products under development may change its specification without notice. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. For the information for microcontroller supports, see the following website. http://edevice.fujitsu./mi/en-support/ Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB96650 Series - FEATURES z Technology 0.18μm CMOS z CPU F2MC-16FX CPU Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) 8-byte instruction execution queue Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available z System clock On-chip PLL clock multiplier (×1 to ×8, ×1 when PLL stop) 4 MHz to 8 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on Q-factor) Up to 16 MHz external clock for devices with fast clock input...