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MBM29DL324TD-80 - 32M (4M x 8/2M x 16) BIT Dual Operation

Download the MBM29DL324TD-80 datasheet PDF. This datasheet also covers the MBM29DL321BD variant, as both devices belong to the same 32m (4m x 8/2m x 16) bit dual operation family and are provided as variant models within a single manufacturer datasheet.

Features

  • 0.33 µm Process Technology.
  • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to Table 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program.
  • Single 3.0 V read, program, and erase Minimizes system level power requirements s.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MBM29DL321BD_FujitsuMediaDevices.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MBM29DL324TD (MBM29DL32xBD) 32M (4M X 8/2M X 16) BIT Dual Operation Fujitsu Media Devices
MBM29DL324TE (MBM29DL32xTE/BE) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT Fujitsu Media Devices
MBM29DL324BD (MBM29DL32xBD) 32M (4M X 8/2M X 16) BIT Dual Operation Fujitsu Media Devices
MBM29DL324BE (MBM29DL32xTE/BE) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT Fujitsu Media Devices
MBM29DL321BD (MBM29DL32xBD) 32M (4M X 8/2M X 16) BIT Dual Operation Fujitsu Media Devices

Other Datasheets by Fujitsu Semiconductor Limited

Part Number Description
MBM29DL324TD-12 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324TD-90 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324BD-12 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324BD-80 32M (4M x 8/2M x 16) BIT Dual Operation
MBM29DL324BD-90 32M (4M x 8/2M x 16) BIT Dual Operation

Full PDF Text Transcription

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20873-4E FLASH MEMORY CMOS 32M (4M × 8/2M × 16) BIT Dual Operation MBM29DL32XTD/BD -80/90/12 s FEATURES • 0.33 µm Process Technology • Simultaneous Read/Write operations (dual bank) Multiple devices available with different bank sizes (Refer to Table 1) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program • Single 3.0 V read, program, and erase Minimizes system level power requirements s PRODUCT LINE UP (Continued) Part No. www.DataSheet4U.com Ordering Part No. VCC = 3.3 V +0.3 V –0.3 V VCC = 3.0 V +0.6 V –0.3 V Max. Address Access Time (ns) Max. CE Access Time (ns) Max.
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