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MBM29F200TC-55 - 2M (256K x 8/128K x 16) BIT FLASH MEMORY

This page provides the datasheet information for the MBM29F200TC-55, a member of the MBM29F200BC 2M (256K x 8/128K x 16) BIT FLASH MEMORY family.

Datasheet Summary

Features

  • Single 5.0 V read, write, and erase Minimizes system level power requirements.
  • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
  • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (Package suffix: PFTN.
  • Normal Bend Type, PFTR.
  • Reversed Bend Type) 44-pin SOP (Package suffix: PF).
  • Minimum 100,000 write/erase cycles.
  • High performance 55 ns maximum access time.
  • Sector erase architecture.

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Datasheet preview – MBM29F200TC-55

Datasheet Details

Part number MBM29F200TC-55
Manufacturer Fujitsu
File Size 565.12 KB
Description 2M (256K x 8/128K x 16) BIT FLASH MEMORY
Datasheet download datasheet MBM29F200TC-55 Datasheet
Additional preview pages of the MBM29F200TC-55 datasheet.

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Full PDF Text Transcription

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FUJITSU SEMICONDUCTOR DATA SHEET DS05-20867-3E FLASH MEMORY CMOS www.datasheet4u.com 2M (256K × 8/128K × 16) BIT MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90 s FEATURES • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase.
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