Datasheet4U Logo Datasheet4U.com

MBM29F400BC-70 - 4M (512K x 8/256K x 16) BIT FLASH MEMORY

This page provides the datasheet information for the MBM29F400BC-70, a member of the MBM29F400BC 4M (512K x 8/256K x 16) BIT FLASH MEMORY family.

Datasheet Summary

Features

  • www. DataSheet4U. com.
  • Single 5.0 V read, write, and erase Minimizes system level power requirements.
  • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
  • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (Package suffix: PFTN.
  • Normal Bend Type, PFTR.
  • Reversed Bend Type) 44-pin SOP (Package suffix: PF).
  • Minimum 100,000 write/erase cycles.
  • High performance 55 ns maximum access time.
  • Sect.

📥 Download Datasheet

Datasheet preview – MBM29F400BC-70

Datasheet Details

Part number MBM29F400BC-70
Manufacturer Fujitsu
File Size 550.03 KB
Description 4M (512K x 8/256K x 16) BIT FLASH MEMORY
Datasheet download datasheet MBM29F400BC-70 Datasheet
Additional preview pages of the MBM29F400BC-70 datasheet.
Other Datasheets by Fujitsu

Full PDF Text Transcription

Click to expand full text
FUJITSU SEMICONDUCTOR DATA SHEET DS05-20851-4E FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT MBM29F400TC-55/-70/-90/MBM29F400BC-55/-70/-90 s FEATURES www.DataSheet4U.com • Single 5.0 V read, write, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) • Minimum 100,000 write/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase.
Published: |