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MBM29LV001BC-55 - 1M (128K x 8) BIT FLASH MEMORY

This page provides the datasheet information for the MBM29LV001BC-55, a member of the MBM29LV001BC 1M (128K x 8) BIT FLASH MEMORY family.

Datasheet Summary

Features

  • Single 3.0 V read, program, and erase Minimizes system level power requirements.
  • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs.
  • Compatible with JEDEC-standard world-wide pinouts 32-pin TSOP(I) (Package suffix: PFTN.
  • Normal Bend Type, PFTR.
  • Reversed Bend Type) 32-pin PLCC (Package suffix: PD).
  • Minimum 100,000 program/erase cycles.
  • High performance 55 ns maximum access time.
  • Sector erase archi.

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Datasheet preview – MBM29LV001BC-55

Datasheet Details

Part number MBM29LV001BC-55
Manufacturer Fujitsu
File Size 421.17 KB
Description 1M (128K x 8) BIT FLASH MEMORY
Datasheet download datasheet MBM29LV001BC-55 Datasheet
Additional preview pages of the MBM29LV001BC-55 datasheet.

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Full PDF Text Transcription

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FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 1M (128K × 8) BIT DS05-20861-3E MBM29LV001TC-55/-70/MBM29LV001BC-55/-70 s FEATURES • Single 3.0 V read, program, and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 32-pin PLCC (Package suffix: PD) • Minimum 100,000 program/erase cycles • High performance 55 ns maximum access time • Sector erase architecture One 8K byte, two 4K bytes, and seven 16K bytes Any combination of sectors can be concurrently erased.
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