Download MBM29LV017-12 Datasheet PDF
MBM29LV017-12 page 2
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MBM29LV017-12 page 3
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MBM29LV017-12 Key Features

  • Address specification is not necessary during mand sequence
  • Single 3.0 V read, program and erase
  • patible with JEDEC-standard mands
  • patible with JEDEC-standard world-wide pinouts
  • Minimum 100,000 program/erase cycles
  • High performance 80 ns maximum access time
  • Sector erase architecture Uniform sectors of 64K bytes each Any bination of sectors can be concurrently erased. Also sup
  • Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector
  • Embedded programTM Algorithms Automatically programs and verifies data at specified address
  • Data Polling and Toggle Bit feature for detection o

MBM29LV017-12 Description

FUJITSU SEMICONDUCTOR DATA SHEET FLASH MEMORY CMOS 16M (2M × 8) BIT DS05-20857-4E MBM29LV017-80/-90/-12.