CDP1877 Description
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ CDP1877, CDP1877C CASCAi5E iR7 iRS iRS IR4 iR3 iRl!
CDP1877 Key Features
- patible with CDP1800 series
- Programmable long branch vector address and vector interval
- 8 levels of interrupt per chip
- Easily expandable
- Latched interrupt requests
- Hard wired interrupt priorities
- Memory mapped
- Multiple chip select inputs to minimize address space requirements