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GS81302S09E - 144Mb SigmaSIO DDR -II Burst of 2 SRAM

This page provides the datasheet information for the GS81302S09E, a member of the GS81302S08E-375 144Mb SigmaSIO DDR -II Burst of 2 SRAM family.

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R/W Read/Write Contol Pin Input Write Active Low; Read Active High NW0 NW1 Synchronous Nybble Writes Input Active Low x08 Version BW0 BW1 Synchronous Byte Writes Input Active Low x18

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

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Datasheet preview – GS81302S09E

Datasheet Details

Part number GS81302S09E
Manufacturer GSI Technology
File Size 496.83 KB
Description 144Mb SigmaSIO DDR -II Burst of 2 SRAM
Datasheet download datasheet GS81302S09E Datasheet
Additional preview pages of the GS81302S09E datasheet.

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Full PDF Text Transcription

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GS81302S08/09/18/36E-375/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaSIOTM DDR -II Burst of 2 SRAM 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
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