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GS8160V36CT - 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs

Download the GS8160V36CT datasheet PDF (GS8160V18CT included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 1m x 18 and 512k x 36 18mb sync burst srams.

Description

Applications The GS8160V18/36CT is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter.

Features

  • FT pin for user-configurable flow through or pipeline operation.
  • Single Cycle Deselect (SCD) operation.
  • 1.8 V +10%/.
  • 10% core power supply.
  • 1.8 V I/O supply.
  • LBO pin for Linear or Interleaved Burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipeline mode.
  • Byte Write (BW) and/or Global Write (GW) operation.
  • Internal self-timed write cycle.
  • Automatic p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8160V18CT_GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8160V36CT
Manufacturer GSI Technology
File Size 598.15 KB
Description 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs
Datasheet download datasheet GS8160V36CT Datasheet

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Full PDF Text Transcription

Click to expand full text
Preliminary GS8160V18/36CT-333/300/250 www.DataSheet4U.com 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 1.8 V +10%/–10% core power supply • 1.8 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • Pb-Free 100-lead TQFP package available 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs 333 MHz–250 MHz 1.8 V VDD 1.8 V I/O cycles can be initiated with either ADSP or ADSC inputs.
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