GSI Technology GS816273CC
18Mb S/DCD Sync Burst SRAMs
FEATURES
● Single/Dual Cycle Deselect selectable● IEEE 1149.1 JTAG-compatible Boundary Scan
● ZQ mode pin for user-selectable high/low output drive
● 3.3 V or 2.5 V core power supply
● 3.3 V or 2.5 V I/O supply
● LBO pin for Linear or Interleaved Burst mode
● Internal input resistors on mode pins allow floating mode pins
● Default to SCD x18/x36 Interleaved Pipeline mode
● Byte Write (BW) and/or Global Write (GW) operation
● Internal self-timed write cycle
● Automatic power-down for portable applications
● JEDEC-standard 209-bump BGA package
● RoHS-compliant 209-bump BGA package available with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. SCD and DCD Pipelined Reads The GS816273CC is an