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GS8180QV36BD - 18Mb Burst of 2 SigmaQuad SRAM

Download the GS8180QV36BD datasheet PDF. This datasheet also covers the GS8180QV18BD-200 variant, as both devices belong to the same 18mb burst of 2 sigmaquad sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol Description SA Synchronous Address Inputs NC No Connect R Synchronous Read W Synchronous Write BW0 BW1 Synchronous Byte Writes BW2 BW3 Synchronous Byte Writes K Input Clock K Input Clock C Output Clock C Output Clock TMS Test Mode Select TDI Test Data Inp

Features

  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual DoubleData Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • 2.5 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.
  • ZQ mode pin for programmable output drive strength.
  • IEEE 1149.1 JTA.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8180QV18BD-200-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8180QV36BD
Manufacturer GSI Technology
File Size 282.51 KB
Description 18Mb Burst of 2 SigmaQuad SRAM
Datasheet download datasheet GS8180QV36BD Datasheet

Full PDF Text Transcription

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GS8180QV18/36BD-200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb Burst of 2 SigmaQuad SRAM 200 MHz–167 MHz 2.5 V VDD 1.8 V or 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual DoubleData Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 2.5 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
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