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GS8182S18BD - 18Mb Burst of 2 SigmaSIO DDR-II SRAM

Download the GS8182S18BD datasheet PDF. This datasheet also covers the GS8182S08BD variant, as both devices belong to the same 18mb burst of 2 sigmasio ddr-ii sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8182S08BD-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8182S18BD
Manufacturer GSI Technology
File Size 522.05 KB
Description 18Mb Burst of 2 SigmaSIO DDR-II SRAM
Datasheet download datasheet GS8182S18BD Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8182S18BGD 18Mb Burst of 2 SigmaSIO DDR-II SRAM
GS8182S18D 18Mb Burst of 2 DDR SigmaSIO-II SRAM
GS8182S08BD 18Mb Burst of 2 SigmaSIO DDR-II SRAM
GS8182S08BGD 18Mb Burst of 2 SigmaSIO DDR-II SRAM
GS8182S09BD 18Mb Burst of 2 SigmaSIO DDR-II SRAM

Full PDF Text Transcription

Click to expand full text
GS8182S08/09/18/36BD-400/375/333/300/250/200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb Burst of 2 SigmaSIO DDR-IITM SRAM 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
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