GS8256418GD-200 Description
Applications The GS8256418/36 is a 301,989,888-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst...
GS8256418GD-200 Key Features
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-patible Boundary Scan
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V +10%/-10% core power supply
- 3.3 V +10%/-10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Byte Write (BW) and/or Global Write (GW) operation