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GS82582DT39GE - 288Mb SigmaQuad-II+ SRAM

Download the GS82582DT39GE datasheet PDF. This datasheet also covers the GS82582DT21GE-675S variant, as both devices belong to the same 288mb sigmaquad-ii+ sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R Synchronous Read Input Active Low W Synchronous Write Input Active Low BWn Synchronous Byte Writes Input Active Low K Input Clock Input Active High K Input Clock Input Active Low Dn Synchronou

Features

  • For use with GSI FPGA-based Controller IP.
  • 3.0 Clock Latency.
  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 4 Read and Write.
  • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V HSTL Interface.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS82582DT21GE-675S-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS82582DT39GE
Manufacturer GSI Technology
File Size 301.67 KB
Description 288Mb SigmaQuad-II+ SRAM
Datasheet download datasheet GS82582DT39GE Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS82582DT21GE 288Mb SigmaQuad-II+ SRAM
GS82582D20GE 288Mb SigmaQuad-II+ SRAM
GS82582D38GE 288Mb SigmaQuad-II+ SRAM
GS82582QT20GE 288Mb SigmaQuad-II+ SRAM
GS82582QT38GE 288Mb SigmaQuad-II+ SRAM

Full PDF Text Transcription

Click to expand full text
165-Bump BGA Commercial Temp Industrial Temp GS82582DT21/39GE-675S/633S/550S 288Mb SigmaQuad-II+ Burst of 4 SRAM Up to 675 MHz 1.8 V VDD 1.5 V I/O Features • For use with GSI FPGA-based Controller IP • 3.0 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.
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