GS8320Z36T-133 Datasheet | GSI Technology

GS8320Z18/36T-250/225/200/166/150/133 100-Pin TQFP mercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAMs 250 MHz- 133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Features - NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-patible with both pipelined and flow through Nt RAM™, No BL™ and ZBT™ SRAMs - 2.5 V or 3.3 V +10%/- 10% core power supply - 2.5 V or 3.3 V I/O supply - User-configurable Pipeline and Flow Through mode - LBO pin for Linear or Interleave Burst mode - Pin patible with 2Mb, 4Mb, 8Mb, and 16Mb devices - Byte write operation (9-bit Bytes) - 3 chip enable signals for easy depth expansion - ZZ Pin for automatic power-down - JEDEC-standard 100-lead TQFP package - Ro HS-pliant 100-lead TQFP package available Functional Description The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, Nt RAM, No BL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates plex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8320Z18/36T may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the...