GSI Technology GS8342D09E-167
The GS8342D08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342D08/18/36E SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.| Part No. | GS8342D09E-167 |
|---|---|
| Datasheet | GS8342D09E-167 Download |
| Manufacturer |  GSI Technology |
| Description | 36Mb SigmaQuad-II Burst |
| Buy | Stock & Price |
FEATURES
● Simultaneous Read and Write SigmaQuad™ Interface● JEDEC-standard pinout and package
● Dual Double Data Rate interface
● Byte Write controls sampled at data-in time
● Burst of 4 Read and Write
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation
● Fully coherent read and write pipelines
● ZQ pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available
● Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices 36Mb SigmaQuad-II Burst of 4 SRAM 167 MHz–333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O SigmaQu...
