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GS8342Q18E-167 - 36Mb SigmaQuad-II Burst of 2 SRAM

Download the GS8342Q18E-167 datasheet PDF. This datasheet also covers the GS8342Q08E-300 variant, as both devices belong to the same 36mb sigmaquad-ii burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Description

Table Symbol SA NC R W BW Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Write BW0 BW3 Synchronous Byte Writes NW0 NW1 Nybble Write Control Pin K Input Clock K Input Clock C Output Clock C Output Clock TMS Test Mode Sel

Features

  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.
  • ZQ pin for programmable output drive strength.
  • IEEE 1149.1 JTAG-co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8342Q08E-300-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8342Q18E-167
Manufacturer GSI Technology
File Size 865.00 KB
Description 36Mb SigmaQuad-II Burst of 2 SRAM
Datasheet download datasheet GS8342Q18E-167 Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8342Q18E-200 36Mb SigmaQuad-II Burst of 2 SRAM
GS8342Q18E-250 36Mb SigmaQuad-II Burst of 2 SRAM
GS8342Q18E-300 36Mb SigmaQuad-II Burst of 2 SRAM
GS8342Q18AE 36Mb SigmaQuad-II Burst of 2 SRAM
GS8342Q18BD-250 36Mb SigmaQuad-II Burst of 2 SRAM

Full PDF Text Transcription

Click to expand full text
Preliminary GS8342Q08/09/18/36E-300/250/200/167 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaQuad-II Burst of 2 SRAM 167 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
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