Datasheet4U Logo Datasheet4U.com

GS8342T08E - 36Mb SigmaCIO DDR-II Burst SRAM

Description

Table Symbol SA NC R/W BW0 BW3 NW0 NW1 LD K K C C TMS TDI TCK TDO VREF ZQ DQ Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read/Write Synchronous Byte Writes Nybble Write Control Pin Synchronous

Features

  • Simultaneous Read and Write SigmaCIO™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36 and x18) and Nybble Write (x8) function.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for progra.

📥 Download Datasheet

Datasheet preview – GS8342T08E

Datasheet Details

Part number GS8342T08E
Manufacturer GSI Technology
File Size 2.33 MB
Description 36Mb SigmaCIO DDR-II Burst SRAM
Datasheet download datasheet GS8342T08E Datasheet
Additional preview pages of the GS8342T08E datasheet.

📁 Similar Datasheet

  • GS8331 - 350KHZ Zero-Drift CMOS Rail-to-Rail IO Opamp (GAINSIL)
  • GS8332 - 350KHZ Zero-Drift CMOS Rail-to-Rail IO Opamp (GAINSIL)
  • GS8334 - 350KHZ Zero-Drift CMOS Rail-to-Rail IO Opamp (GAINSIL)
  • GS8000 - DVI / HDMI Extender (Gennum Corporation)
  • GS8041 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8042 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8043 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8043NH - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8043NL - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8051 - 250MHZ CMOS Rail-to-Rail Output Opamps (GAINSIL)
Other Datasheets by GSI Technology

Full PDF Text Transcription

Click to expand full text
Preliminary GS8342T08/09/18/36E-333/300/267*/250/200/167 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
Published: |