GS8662D10BD Datasheet | GSI Technology

Features - 2.0 Clock Latency - Simultaneous Read and Write Sigma Quad™ Interface - JEDEC-standard pinout and package - Dual Double Data Rate interface - Byte Write controls sampled at data-in time - Burst of 4 Read and Write - On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs - 1.8 V +100/- 100 m V core power supply - 1.5 V or 1.8 V HSTL Interface - Pipelined read operation - Fully coherent read and write pipelines - ZQ pin for programmable output drive strength - Data Valid Pin (QVLD) Support - IEEE 1149.1 JTAG-pliant Boundary Scan - 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package - Ro HS-pliant 165-bump BGA package available Sigma Quad™ Family Overview The GS8662D07/10/19/37BD are built in pliance with the Sigma Quad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662D07/10/19/37BD Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS8662D07/10/19/37BD Sigma Quad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a Sigma Quad-II+ B4 RAM is four times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate ining data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore the address field of a Sigma Quad-II+ B4 RAM is always two address pins less than the advertised index depth (e.g., the 8M x 8 has a 2M addressable index). t KHKH t KHQV -450 2.22 ns 0.45 ns Parameter Synopsis -400 2.5 ns 0.45 ns -350 2.86 ns...