GS8662Q36E-250 Datasheet | GSI Technology

Preliminary GS8662Q08/09/18/36E-300/250/200/167 .. 165-Bump BGA mercial Temp Industrial Temp Features - Simultaneous Read and Write Sigma Quad™ Interface - JEDEC-standard pinout and package - Dual Double Data Rate interface - Byte Write controls sampled at data-in time - Burst of 2 Read and Write - 1.8 V +100/- 100 m V core power supply - 1.5 V or 1.8 V HSTL Interface - Pipelined read operation - Fully coherent read and write pipelines - ZQ pin for programmable output drive strength - IEEE 1149.1 JTAG-pliant Boundary Scan - Pin-patible with present 9Mb, 18Mb, and 36Mb and future 144Mb devices - 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package - Ro HS-pliant 165-bump BGA package available 72Mb Sigma Quad-II Burst of 2 SRAM 300 MHz- 167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O Sigma Quad-II B2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Sigma Quad-II B2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 2048K addressable index). Sigma Quad™ Family Overview The GSQ8662Q08/09/18/36E are built in pliance with the Sigma Quad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GSQ8662Q08/09/18/36E Sigma Quad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GSQ8662Q08/09/18/36E Sigma Quad-II SRAMs are synchronous devices....