Datasheet4U Logo Datasheet4U.com

GS8662R08E - 72Mb SigmaDDR-II Burst of 4 SRAM

Features

  • Simultaneous Read and Write SigmaDDR-II™ Interface.
  • Common I/O bus.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write (x36 and x18) and Nybble Write (x8) function.
  • Burst of 4 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation with self-timed Late Write.
  • Fully coherent read and write pipelines.
  • ZQ pin for pro.

📥 Download Datasheet

Datasheet preview – GS8662R08E

Datasheet Details

Part number GS8662R08E
Manufacturer GSI Technology
File Size 1.01 MB
Description 72Mb SigmaDDR-II Burst of 4 SRAM
Datasheet download datasheet GS8662R08E Datasheet
Additional preview pages of the GS8662R08E datasheet.

📁 Similar Datasheet

  • GS8631 - 6-MHZ CMOS Rail-to-Rail I/O Opamps (GAINSIL)
  • GS8631N - 6-MHZ CMOS Rail-to-Rail I/O Opamps (GAINSIL)
  • GS8631Y - 6-MHZ CMOS Rail-to-Rail I/O Opamps (GAINSIL)
  • GS8632 - 6-MHZ CMOS Rail-to-Rail I/O Opamps (GAINSIL)
  • GS8634 - 6-MHZ CMOS Rail-to-Rail I/O Opamps (GAINSIL)
  • GS864272C-xxxV - (GS8642xxB/C-xxxV) 4M x 18 ( 2M x 36)
  • GS8000 - DVI / HDMI Extender (Gennum Corporation)
  • GS8041 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8042 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
  • GS8043 - 14.5KHZ CMOS Rail-to-Rail I/O Opamp (GAINSIL)
Other Datasheets by GSI Technology

Full PDF Text Transcription

Click to expand full text
Not Recommended for New Design—Discontinued Product GS8662R08/09/18/36E-250/200/167 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaDDR-II™ Burst of 4 SRAM 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR-II™ Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • IEEE 1149.
Published: |