GS8662S08BGD Datasheet PDF (72Mb SigmaSIO DDR -II Burst of 2 SRAM)

GS8662S08BGD - 72Mb SigmaSIO DDR -II Burst of 2 SRAM

This page provides the datasheet information for the GS8662S08BGD, a member of the GS8662S08BD 72Mb SigmaSIO DDR -II Burst of 2 SRAM family.

Features

Simultaneous Read and Write SigmaSIO™ Interface.
JEDEC-standard pinout and package.
Dual Double Data Rate interface.
Byte Write controls sampled at data-in time.
DLL circuitry for wide output data valid window and future frequency scaling.
Burst of 2 Read and Write.
1.8 V +100/.
100 mV core power supply.
1.5 V or 1.8 V HSTL Interface.
Pipelined read operation.
Fully coherent read and write pipelines.

Datasheet Details

Part number	GS8662S08BGD
Manufacturer	GSI Technology
File Size	463.74 KB
Description	72Mb SigmaSIO DDR -II Burst of 2 SRAM
Datasheet	GS8662S08BGD Datasheet
Additional preview pages of the GS8662S08BGD datasheet.

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Full PDF Text Transcription

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GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.

Published: Oct 14, 2016 |