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GS8662S18E-333 - DDR SigmaSIO-II SRAM

This page provides the datasheet information for the GS8662S18E-333, a member of the GS8662S08E-333 DDR SigmaSIO-II SRAM family.

Description

Table Symbol SA NC R/W NW0 NW1 BW0 BW1 BW0 BW3 K C TMS TDI TCK TDO VREF ZQ K C DOFF LD CQ CQ Dn Qn VDD VDDQ VSS Description Synchronous Address Inputs No Connect Read/Write Contol Pin Synchronous Nybble Writes Synchronous Byte Writes Synchronous Byte Writes Input Clock Outpu

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

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Datasheet preview – GS8662S18E-333

Datasheet Details

Part number GS8662S18E-333
Manufacturer GSI Technology
File Size 2.29 MB
Description DDR SigmaSIO-II SRAM
Datasheet download datasheet GS8662S18E-333 Datasheet
Additional preview pages of the GS8662S18E-333 datasheet.

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Full PDF Text Transcription

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Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
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