Datasheet4U Logo Datasheet4U.com

GS8662S36BGD - 72Mb SigmaSIO DDR -II Burst of 2 SRAM

Download the GS8662S36BGD datasheet PDF. This datasheet also covers the GS8662S08BD variant, as both devices belong to the same 72mb sigmasio ddr -ii burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • Simultaneous Read and Write SigmaSIO™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Burst of 2 Read and Write.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully coherent read and write pipelines.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8662S08BD-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8662S36BGD
Manufacturer GSI Technology
File Size 463.74 KB
Description 72Mb SigmaSIO DDR -II Burst of 2 SRAM
Datasheet download datasheet GS8662S36BGD Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
GS8631 6-MHZ CMOS Rail-to-Rail I/O Opamps GAINSIL
GS8631N 6-MHZ CMOS Rail-to-Rail I/O Opamps GAINSIL
GS8631Y 6-MHZ CMOS Rail-to-Rail I/O Opamps GAINSIL
GS8632 6-MHZ CMOS Rail-to-Rail I/O Opamps GAINSIL
GS8634 6-MHZ CMOS Rail-to-Rail I/O Opamps GAINSIL

Other Datasheets by GSI Technology

Part Number Description
GS8662S36BD 72Mb SigmaSIO DDR -II Burst of 2 SRAM
GS8662S36E-167 DDR SigmaSIO-II SRAM
GS8662S36E-200 DDR SigmaSIO-II SRAM
GS8662S36E-250 DDR SigmaSIO-II SRAM
GS8662S36E-300 DDR SigmaSIO-II SRAM

Full PDF Text Transcription

Click to expand full text
GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.
Published: |