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GS8662TT06BD - 72Mb SigmaDDR-II+ Burst of 2 SRAM

Download the GS8662TT06BD datasheet PDF. This datasheet also covers the GS8662TT20BD variant, as both devices belong to the same 72mb sigmaddr-ii+ burst of 2 sram family and are provided as variant models within a single manufacturer datasheet.

Features

  • 2.5 Clock Latency.
  • Simultaneous Read and Write SigmaDDRTM Interface.
  • JEDEC-standard pinout and package.
  • Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 2 Read and Write.
  • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fu.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8662TT20BD-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8662TT06BD
Manufacturer GSI Technology
File Size 240.96 KB
Description 72Mb SigmaDDR-II+ Burst of 2 SRAM
Datasheet download datasheet GS8662TT06BD Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS8662TT06BGD 72Mb SigmaDDR-II+ Burst of 2 SRAM
GS8662TT11BD 72Mb SigmaDDR-II+ Burst of 2 SRAM
GS8662TT11BGD 72Mb SigmaDDR-II+ Burst of 2 SRAM
GS8662TT20BD 72Mb SigmaDDR-II+ Burst of 2 SRAM
GS8662TT20BGD 72Mb SigmaDDR-II+ Burst of 2 SRAM

Full PDF Text Transcription

Click to expand full text
165-Bump BGA Commercial Temp Industrial Temp GS8662TT20/38BD-550/500/450/400/350 GS8662TT06/11BD-500/450/400/350 72Mb SigmaDDRTM-II+ Burst of 2 SRAM 550 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package • Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.
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