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GS880F18AT-7 - 9Mb Synchronous Burst SRAMs

This page provides the datasheet information for the GS880F18AT-7, a member of the GS880F18AT-55 9Mb Synchronous Burst SRAMs family.

Datasheet Summary

Description

Applications The GS880F18/32/36AT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter.

Features

  • Flow Through mode operation; Pin 14 = No Connect.
  • 2.5 V or 3.3 V +10%/.
  • 10% core power supply.
  • 2.5 V or 3.3 V I/O supply.
  • LBO pin for Linear or Interleaved Burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipeline mode.
  • Byte Write (BW) and/or Global Write (GW) operation.
  • Internal self-timed write cycle.
  • Automatic power-down for portable.

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Datasheet preview – GS880F18AT-7

Datasheet Details

Part number GS880F18AT-7
Manufacturer GSI Technology
File Size 598.17 KB
Description 9Mb Synchronous Burst SRAMs
Datasheet download datasheet GS880F18AT-7 Datasheet
Additional preview pages of the GS880F18AT-7 datasheet.

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Full PDF Text Transcription

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GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5 100-Pin TQFP Commercial Temp Industrial Temp Features • Flow Through mode operation; Pin 14 = No Connect • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package 512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs www.DataSheet4U.com 5.5 ns–8.5 ns 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used.
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