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GS88418B Datasheet PDF

GSI Technology GS88418B

The GS88436B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
Part No. GS88418B
Datasheet GS88418B Download
Manufacturer
GSI Technology
Description S/DCD Sync Burst SRAMs
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GS88418B datasheet page 1 preview

FEATURES

● FT pin for user-configurable flow through or pipelined operation
● Single/Dual Cycle Deselect Selectable
● ZQ mode pin for user-selectable high/low output drive strength
● 3.3 V +10%/–5% core power supply
● 2.5 V or 3.3 V I/O supply
● LBO pin for Linear or Interleaved Burst mode
● Internal input resistors on mode pins allow floating mode pins
● Default to SCD x18/x36 Interleaved Pipeline mode
● Byte Write (BW) and/or Global Write (GW) operation
● Common data inputs and data outputs
● Clock Control, registered, address, data, and control
● Internal self-timed write cycle
● Automatic power-down for portable applications
● 119-bump BGA package 512K x 18, 256K x 36 8Mb S/DCD Sync Burst SRAMs Flow Through/Pipeline Reads 200 MHz–133 MHz 3.3 V VDD 3.3 V and 2.5 V I/O (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode bump (Bump 5R).
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