GS816132B Datasheet | GSI

.. GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) 100-Pin TQFP & 165-Bump BGA mercial Temp Industrial Temp Features - FT pin for user-configurable flow through or pipeline operation - Single Cycle Deselect (SCD) operation - IEEE 1149.1 JTAG-patible Boundary Scan - 2.5 V or 3.3 V +10%/- 10% core power supply - 2.5 V or 3.3 V I/O supply - LBO pin for Linear or Interleaved Burst mode - Internal input resistors on mode pins allow floating mode pins - Default to Interleaved Pipeline mode - Byte Write (BW) and/or Global Write (GW) operation - Internal self-timed write cycle - Automatic power-down for portable applications - JEDEC-standard 100-lead TQFP 100-pin TQFP and 165-bump BGA packages - Ro HS-pliant 100-pin TQFP and 165-bump BGA packages available 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 250 MHz- 150 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect mands one stage less than read mands. SCD RAMs begin turning off their outputs immediately after the deselect mand has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input bined with one or more individual byte write signals (Bx). In addition,...