GS816136B Description
Applications The GS816118B(T/D)/GS816132B(D)/GS816136B(T/D) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os.
GS816136B Key Features
- FT pin for user-configurable flow through or pipeline operation
- Single Cycle Deselect (SCD) operation
- IEEE 1149.1 JTAG-patible Boundary Scan
- 2.5 V or 3.3 V +10%/-10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle