GX28E01-100
Description
The GX28E01-100 bines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations.
Key Features
- 1024 bits of EEPROM memory partitioned into four pages of 256 bits
- On-chip 512-bit SHA-1 engine to pute 160-bit Message Authentication Codes (MAC) and to generate secrets
- Write access requires knowledge of the secret and the capability of puting and transmitting a 160-bit MAC as authorization
- User-programmable page write-protection for page 0, page 3 or all four pages together
- User-programmable OTP EPROM emulation mode for page 1 ("write to 0")
- municates to host with a single digital signal at 15.3k bits or 125k bits per second using 1-Wire protocol
- Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise
- Reads and writes over a wide voltage range of 2.8V to 5.25V from -40°C to +85°C
