Datasheet Details
| Part number | GL9711 |
|---|---|
| Manufacturer | Genesys Logic |
| File Size | 396.75 KB |
| Description | PCI Express PIPE x1 PHY |
| Datasheet | GL9711-GenesysLogic.pdf |
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Overview: Genesys Logic, Inc. GL9711 PCI ExpressTM PIPE x1 PHY Datasheet Revision 1.10 Jul. 04, 2006 GL9711 PCI ExpressTM PIPE x1 PHY Copyright: Copyright © 2006 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic Inc.. Disclaimer: ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE. Trademarks: is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://.genesyslogic. ©2000-2006 Genesys Logic Inc. - All rights reserved. Page 2 GL9711 PCI ExpressTM PIPE x1 PHY Revision History Revision 0.95 0.96 0.97 0.98 1.00 1.01 1.02 1.
| Part number | GL9711 |
|---|---|
| Manufacturer | Genesys Logic |
| File Size | 396.75 KB |
| Description | PCI Express PIPE x1 PHY |
| Datasheet | GL9711-GenesysLogic.pdf |
|
|
|
7/11/2005 7/27/2005 09/20/2005 11/15/2005 12/15/2005 04/13/2006 04/26/2006 07/04/2006 Preliminary release 1.
Modify Table3.1–Ball Out, p.11 2.
Modify “PIPE Interface” and “Other Signals”, Table3.4–Pin Descriptions, p.15~p.17 3.
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