Datasheet Summary
DDR4 SDRAM
GDQ2BFAA DATASHEET
DS-00808-GDQ2BFAA-Rev1.5
1
September 2022
DDR4 SDRAM
1 Features
- Power supply: VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)
- JEDEC standard package: 96-Ball FBGA (x16)
- Array Configuration: 8 Banks (x16) 2 groups of 4 banks
- 8n-Bit prefetch architecture
- Burst Length (BL): 8 and 4 with Burst Chop (BC)
- Programmable CAS Latency (CL)
- Programmable CAS Write Latency (CWL)
- Internal generated VREF for data inputs
- Data Mask (DM) for write data
- On-Die Termination (ODT): Support Nominal, Park and Dynamic ODT
- Interface: 1.2V Pseudo Open Drain (POD) IO
- Differential clock and data strobe inputs (CK_t ,CK_c;...